The present disclosure relates to semiconductor devices and electronic devices, and more particularly, to semiconductor devices including a semiconductor integrated circuit element and a BGA substrate on which the semiconductor integrated circuit element is mounted, and electronic devices including the semiconductor devices.
In order to reduce the size and cost of an electronic apparatus which processes high-speed and high-resolution moving images, such as a high-definition digital television, all functions may be integrated into a single semiconductor chip. Therefore, microfabrication technology has been advanced for wafer processing of semiconductor elements, leading to a reduction in chip area. It is, however, necessary to enable a so-called system LSI (system on a chip) to process images in a high-definition digital television while transmitting and receiving a large amount of data to and from a peripheral memory element. In this case, the data transfer rate between the memory element and the system LSI is typically becoming 1.3 Gbps or more.
Examples of a mainstream packaging for a system LSI are a plastic ball grid array (P-BGA) package, which employs wire bonding, and a flip chip BGA (FCBGA) package, which employs solder bumps etc. These packages are capable of providing a large number of input and output signal lines and supplying large or various powers.
There is also a demand for a smaller semiconductor device incorporated in an electronic apparatus in order to reduce the area of the semiconductor device mounted on an interconnect substrate. In an effort to meet these requirements, for example, a system-in-a-package (hereinafter referred as an “SiP”), which is a plurality of semiconductor chips enclosed in a single package, has been employed.
High-speed multi-bit data transfer between a plurality of memories may be achieved in a semiconductor device as follows. Semiconductor chips are connected together using short interconnects to reduce a signal delay time, thereby reducing a degradation in the performance of the mounted semiconductor chips and an increase in the areas of the chips mounted on the substrate in the semiconductor device. Specifically, there is a proposed semiconductor device (a system-in-a-package or a multi-chip package) in which each memory element is provided with a plurality of chip interconnect pads for interfacing with signal interconnects input and output in common between the memory elements, and a plurality of pads for receiving signals (e.g., a data signal, an address signal, a control signal, etc.) required for operation of the memory element are arbitrarily connected to the chip interconnect pads via interconnects in each memory element. In the semiconductor device, by connecting the memory elements in series using these pads and external interconnects, the length of the interconnect between each semiconductor chip can be reduced, whereby the signal delay time can be reduced, and therefore, a degradation in the performance of the mounted semiconductor chips and an increase in the area of the chips mounted on the semiconductor device can be reduced (see, for example, Japanese Patent Publication No. 2006-49586).